Schematics to configure Cyclone GX by Parallel Flash Loader (MAX II+NOR Flash Memory)

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I need to configure Cyclone GX in PS mode by Parallel Flash Loader residing inside MAX II with configuration data inside NOR Flash Memory.

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The Cyclone IV GX Starter Kit has PS configuration (and an option for AS configuration).

http://www.altera.com/products/devkits/altera/kit-cyclone-iv-starter.html

I've uploaded the schematic that is contained within the installation file.

Cheers,

Dave

Thanks, this is what I've been looking for!

In Cyclone IV GX Transceiver Starter Kit EPM2210 is used to configure Cyclone IV GX and olso does many other things.

Can I use a cheaper MAX II EPM240 instead of expensive EPM2210 just to configure Cyclone IV GX?

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In Cyclone IV GX Transceiver Starter Kit EPM2210 is used to configure Cyclone IV GX and olso does many other things.

Can I use a cheaper MAX II EPM240 instead of expensive EPM2210 just to configure Cyclone IV GX?

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Probably. Create a top-level design with the PFL component configured for whatever flash you are planning on using and synthesize it.

If the PFL component supports QSPI (Quad SPI) flash, then look at using that, rather than parallel flash. The interface requires only 5-6 pins and its fast enough to meet the PS controller timing; data can be read from the flash in quad-bit mode and then serialized to the PS interface.

Cheers,

Dave

In the "Parallel Flash Loader Megafunction User Guide" section "Specifications" on page 46 there are equations to estimate the time for reconfiguring the FPGA with the PFL megafunction.

In the Table 15 Ccfg is calculated from DCLK Ratio, but in the following examples Ccfg is always equal to 2.5.

Why? Is it an error?

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In the "Parallel Flash Loader Megafunction User Guide" section "Specifications" on page 46 there are equations to estimate the time for reconfiguring the FPGA with the PFL megafunction.

In the Table 15 Ccfg is calculated from DCLK Ratio, but in the following examples Ccfg is always equal to 2.5.

Why? Is it an error?

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Lets see ...

http://www.altera.com/literature/ug/ug_pfl.pdf

The example on p48 starts by stating that DCLK ratio = 2, so the later use of Ccfg = 2.5 appears to be an error. File a Service Request with Altera and ask them to fix their documentation.

Cheers,

Dave

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What is the reason for putting PCIe into JTAG chain in Cyclone IV GX Starter Kit and similar schematics?

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If you look at the schematic, you'll see that the PCIe JTAG signals actually connect through a bus switch, so the diagram is incorrect (it shows the MAX II connected to the PCIe).

The implementation could allow a PCIe JTAG master to access the board JTAG chain. However, I've never seen a motherboard that provided JTAG access to PCIe slots, so its rarely used.

Cheers,

Dave

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What can be the cause for that error?

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Sorry, I don't use the PFL core. The earlier versions of the core could not be simulated, so I wrote my own.

You'll have to file a Service Request to ask why it does not work.

Cheers,

Dave