Schematics to configure Cyclone GX by Parallel Flash Loader (MAX II+NOR Flash Memory)

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In the "Parallel Flash Loader Megafunction User Guide" section "Specifications" on page 46 there are equations to estimate the time for reconfiguring the FPGA with the PFL megafunction.

In the Table 15 Ccfg is calculated from DCLK Ratio, but in the following examples Ccfg is always equal to 2.5.

Why? Is it an error?

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Lets see ...

http://www.altera.com/literature/ug/ug_pfl.pdf

The example on p48 starts by stating that DCLK ratio = 2, so the later use of Ccfg = 2.5 appears to be an error. File a Service Request with Altera and ask them to fix their documentation.

Cheers,

Dave