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Altera_Forum
Honored Contributor
12 years agoIn the "Parallel Flash Loader Megafunction User Guide" section "Specifications" on page 46 there are equations to estimate the time for reconfiguring the FPGA with the PFL megafunction.
In the Table 15 Ccfg is calculated from DCLK Ratio, but in the following examples Ccfg is always equal to 2.5. Why? Is it an error?