Honored Contributori want to ask you the usage of the scfifo megafunction as a for example input buffer for an sopc component in cyclon2 device.
specifically i want to ask the usage of the signals rdreq and wrreq of it for ordinary operation,that is,first writing the data inputs to the memory and then seeing them on the q output of the component which has scfifo in it. best, thanx in advance..
Honored ContributorHi,
I assume scfifo stands for single clk fifo. You can see the description of the fifo signals in the help(megawizard). Generally this applies (but check your fifo): when you want to write data then wrreq should be high. Data coincindental with high wrreq(at clk edge) is written into fifo. when you want to read data out then rdreq should be high and then oldest data is read out (like a queue) and becomes available on next clk edge.(avoid empty or full fifo). There might be issues with which clk edge(rising/falling) is relevant so check your fifo information. Any clock enable should be accounted for.Honored Contributorthanx kaz,yes scfifo is that u understood.
my problem was in the simulation in quartus but the problem was the manipulation of the wrreq and rdreq for the rising clock edge of the clock,that is, the clock must see the wrreq or rdreq' values @ its positive clock edge as u mentioned,if not, u may not see the ordinary operation. So,now i m ok with the scfifo's usage.
