scfifo of altera_mf

Hi,

I assume scfifo stands for single clk fifo.

You can see the description of the fifo signals in the help(megawizard).

Generally this applies (but check your fifo):

when you want to write data then wrreq should be high. Data coincindental with high wrreq(at clk edge) is written into fifo.

when you want to read data out then rdreq should be high and then oldest data is read out (like a queue) and becomes available on next clk edge.(avoid empty or full fifo).

There might be issues with which clk edge(rising/falling) is relevant so check your fifo information. Any clock enable should be accounted for.