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Altera_Forum
Honored Contributor
Honored Contributorscfifo of altera_mf
i want to ask you the usage of the scfifo megafunction as a for example input buffer for an sopc component in cyclon2 device. specifically i want to ask the usage of the signals rdreq and wrreq...
Altera_ForumHonored Contributor
Honored Contributorthanx kaz,yes scfifo is that u understood.
my problem was in the simulation in quartus but the problem was the manipulation of the wrreq and rdreq for the rising clock edge of the clock,that is, the clock must see the wrreq or rdreq' values @ its positive clock edge as u mentioned,if not, u may not see the ordinary operation. So,now i m ok with the scfifo's usage.
