Forum Discussion
Honored ContributorScaling core clock of 100MHz to 23MHz & 20MHz
Hello All,
I am using Altera Stratix II for my project. I have generated a PLL in LVDs mode(for a deserialization factor of 10 and date rates is 1000Mbps). The two available clock sources on the board are 100MHz and 62.5MHz. I need to generate 23MHz and 20MHz MHz clocks for a module in my project. When I try to generate a PLL in LVDs mode in Mega Core Wizard, by default it selects a FAST PLL and the minimum output frequency is 33.3333MHz. Can I use any other logic and generate a 23MHz and 20MHz clock from 100MHz core clock. Can any one of you suggest a solution to this problem. Many thanks in advance,34 Replies
Altera_ForumYa, I am using an Enhanced Pll to get a 23MHz clock with an input of 100MHz(Slow Clock from FPLL) It works. On the receiver end I am receiving the data, and with the same 23MHz clk i am storing the data into RAM.
I am sending a 10 bit constant value from Sender to Receiver but the thing is data sampling is not proper for example if i send : Sender 01 0011 0101 Receiver 11 0101 0100 (RAM) Sender 11 0011 0100 Receiver 10 1001 1001 (RAM) I think I need some kind of data training patterns. Could you please suggest me so ideas?- Altera_Forum
Yes, I overlooked the 1000 MHz data rate. But then I didn't clearly understand how the 20 or 23 MHz clock is related to LVDS transmission? If it isnt'n at all, you can use a separate PLLs to generate the clocks.
A 20 MHz clock could be used as input or output frame clock for 100/1000 MHz LVDS channel (I don't see a similar purpose for a 23 MHz clock). But it can't be generated or received by the LVDS PLL directly, apparently due to restriction of available scale factors. So you have to use additional PLLs. Synchronisation shouldn't be an issue as long as the 100 MHz LVDS slow clock is the inclk for both PLLs. For source synchronous reception with 20 MHz input clock, a 20/100 MHz PLL must be used in front of the LVDS receiver. Using DPA hopefully cancels all problems with additional delays. - Altera_Forum
thku, date rates is 1000Mbps
- Altera_Forum
I don't know how you got a minimum output frequency of 33 MHz. I understand, that your LVDS units have data rate of 200/230 MHz or a slow clock of 20/23 Mhz respectively. By using the LVDS Megawizard, you see that the 200 MHz LVDS can operate from a 100 MHz inclock but the 230 MHz can't. It would need e. g. 23 or 115 MHz inclock. So you need cascaded PLLs, but they are available with Stratix II.
