Scaling core clock of 100MHz to 23MHz & 20MHz

Yes, I overlooked the 1000 MHz data rate. But then I didn't clearly understand how the 20 or 23 MHz clock is related to LVDS transmission? If it isnt'n at all, you can use a separate PLLs to generate the clocks.

A 20 MHz clock could be used as input or output frame clock for 100/1000 MHz LVDS channel (I don't see a similar purpose for a 23 MHz clock). But it can't be generated or received by the LVDS PLL directly, apparently due to restriction of available scale factors. So you have to use additional PLLs. Synchronisation shouldn't be an issue as long as the 100 MHz LVDS slow clock is the inclk for both PLLs.

For source synchronous reception with 20 MHz input clock, a 20/100 MHz PLL must be used in front of the LVDS receiver. Using DPA hopefully cancels all problems with additional delays.