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Altera_Forum
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17 years ago

Scaling core clock of 100MHz to 23MHz & 20MHz

Hello All, I am using Altera Stratix II for my project. I have generated a PLL in LVDs mode(for a deserialization factor of 10 and date rates is 1000Mbps). The two available clock sources ...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Ya, I am using an Enhanced Pll to get a 23MHz clock with an input of 100MHz(Slow Clock from FPLL) It works. On the receiver end I am receiving the data, and with the same 23MHz clk i am storing the data into RAM.

I am sending a 10 bit constant value from Sender to Receiver but the thing is data sampling is not proper for example if i send :

Sender 01 0011 0101 Receiver 11 0101 0100 (RAM)

Sender 11 0011 0100 Receiver 10 1001 1001 (RAM)

I think I need some kind of data training patterns. Could you please suggest me so ideas?