Scaling core clock of 100MHz to 23MHz & 20MHz

Thanku. Ya I am using a DPA block and an external PLL(in LVDS mode). The slow clock is phaseshifter with the input clock by 4.5deg and Serial clock at data rate by 45deg respectively. I am completly new to this DPA. Can i know, whether the data alignment is possible without using a training patern or the otherway arroung could u please tell me what acctually u ment by

"If your application has stable LVDS data phase and executing a train phase is unsuitable, then you can adjust the phase manually. An adjustment beyond a bit time duration can be achieved with an external PLL. Alternatively, the channel alignment input could be used to shift the data by a fixed number of bits and the 360° inclk adjustment can center the bit sampling to input data."

reg

sa