Scaling core clock of 100MHz to 23MHz & 20MHz

I haven't been using Stratix II respectively Arria GX LVDS receiver without DPA and word alignment, so I'm not sure about the initial inclk to data alignment. But it seems, as it has a built-in slowclock phase shift. The results are not as expected with the word boundary aligned to inclk rising edge.

The disadvantage with DPA and data realignment is the need to coordinate train pattern send time (and some additional design complexity). Your test data would be e. g. suited as train pattern. After DPA reset, first step is adjustment of bit phase by DPA. With usual binary data, the DPA circuitry must be disabled in normal operation, cause no edges are present in case of all zero or all one data. During word alignment step, the channel alignment input is pulsed until the train pattern matches.

If your application has stable LVDS data phase and executing a train phase is unsuitable, then you can adjust the phase manually. An adjustment beyond a bit time duration can be achieved with an external PLL. Alternatively, the channel alignment input could be used to shift the data by a fixed number of bits and the 360° inclk adjustment can center the bit sampling to input data.