Forum Discussion
Honored Contributorrx_freqlocked signal on Cyclone IV GX
I'm seeing strange behavior from the rx_freqlocked signal that's output from the Cyclone IV transceiver block in basic mode.
According to the transceiver documentation: --- Quote Start --- In automatic lock mode, the switch from LTR to LTD states is indicated by the assertion of the rx_freqlocked signal and the switch from LTD to LTR states indicated by the de-assertion of the rx_freqlocked signal. --- Quote End --- However, I'm seeing this signal asserted even when there's no data available at the receiver for the for the CDR to lock to. Clearly I'm not understanding exactly what this signal is telling me. Does anyone have some insight on this? Thanks13 Replies
Altera_ForumAre you seeing it toggle or remain asserted? In my experience this signal toggles (not necessarily every clock cycle) while the state machine attempts to lock to data. Depending on your device there's a Tltd_auto in the 4us range and the rx_freqlocked should be considered asserted only after it has remained high w/o transition for this amount of time.
- Altera_Forum
Thanks for the suggestion.
It seems to be constantly asserted, but I'll double check that. I found a knowledge base article that seems to describe the problem I'm seeing: http://http://www.altera.com/support/kdb/solutions/rd12152010_565.html (http://http//www.altera.com/support/kdb/solutions/rd12152010_565.html) This article indicates that the problem was caused by a bug in Quartus 10.1 and it links to a patch that fixes the problem. I'm using 11.0sp1, so hopefully that bug has been fixed. At any rate, there's no patch listed for 11.0sp1. I submitted a service request on this and will post here if I find anything out from that route. - Altera_Forum
After a month the results of my service request have been unfruitful. the rx_freqlocked signal seems to be simply broken in my system.
I'm using Quartus 11.0sp1 on a Cyclone IV GX device. The altgxb is in basic mode. Does this signal work for anyone? What I'm seeing is the signal goes active after the receive analog reset is deasserted. It remains active no matter what happens on the data line. This is running in automatic lock mode. I've tried manual lock mode, but the signal behaves the same no matter what I do with the locktodata and locktoref lines. It indicates locked after releasing analog reset and remains stuck high no matter how I chance those inputs. If anyone has any insight into this it would be greatly appreciated! S - Altera_Forum
I'm bumping this thread in hopes that someone out there has some insight on my problem.
I've been working on this system for a couple months now, and the rx_freqlocked signal is still completely non-functional no matter what I do. Altera support is useless. Has anyone been able to get the rx_freqlocked signal to work on a Cyclone IV GX? - Altera_Forum
if the SR is still open, ask for confirmation that the "SPR" was fixed in releases after 10.1
- Altera_Forum
Thanks for the suggestion.
One of the first things I pointed out to the support team in my service request was the fact that there was a known bug listed for 10.1 which described the exact problem I'm seeing. I asked if that bug was fixed in 11.0, but that question was never answered. I'm quite disheartened by the response I've gotten from Altera support on this issue. It's been two months since the SR was open and, aside from trying to close the request I received little response from my support engineer. I'm considering opening a different request on the same issue in hopes that it gets assigned to someone else. - Altera_Forum
I have the same exact problem. I am tempted to move back to 10.1 and install th service pack to see if that works.
I don't care to much about the rx_freqlocked signal. It's just my design works half the time. Sometime it starts up and works and continues to work, and sometimes it starts up and doesn't receive anything. I am assuming it doesn't lock to the correct signal?? or the reset sequence is messed up. But if the rx_freqlocked signal is not working properly then it's possible something else isn't working. - Altera_Forum
other than the rx_freqlocked did you get it to work? like I said half the time I power up and I can send and recieve data and the other half it doesn't receive.
- Altera_Forum
Hi Jon, sorry for the delayed response. I haven't been checking back here.
Yes, other then the rx_freqlocked signal, the high speed serial interface seems to be working fine for me. Finally, after 4.5 months of the service request being opened, the support engineer has decided to try to look into the problem. I'll post back if it ever gets resolved. - Altera_Forum
I got my circuit to work. I justed ignored the rx_freqlocked signal. I used an external signal detect to cause it to manually lock.
