Forum Discussion
Mikhail_a
Occasional Contributor
Occasional ContributorRVALID is high after reset on Agilex 7 M-series F2H bridge
Hello I work with Agilex 7 M-series device and I see a strange behavior of F2H bridge. I see that after deasserting f2h rst_n RVALID and BVALID signal go high, also I see some data coming from RDATA...
tehjingy_Altera
Regular Contributor
Regular ContributorHi
For the burst length the Agilex7 support up to 16 transaction for the burst transaction as u refer below:
It seems like in your last reply you mentioned that you are able to communicate through the FPGA2HPS without any issues.
Are there any other issues before we close this case?
Regards
Jingyang, Teh
Mikhail_aOccasional Contributor
Occasional ContributorHi
Unfortunately as you can see there is an AXI4 spec violation as ARLEN is not zero and the number of returned data beats corresponds to ARLEN == 0
So I cant say the bridge works correctly
