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Occasional Contributor

2 years ago

RVALID is high after reset on Agilex 7 M-series F2H bridge

Hello I work with Agilex 7 M-series device and I see a strange behavior of F2H bridge. I see that after deasserting f2h rst_n RVALID and BVALID signal go high, also I see some data coming from RDATA...

Configuration

tehjingy_Altera

Regular Contributor

2 years ago

For the burst length the Agilex7 support up to 16 transaction for the burst transaction as u refer below:

https://www.intel.com/content/www/us/en/docs/programmable/683567/23-1/fpga-to-hps-bridge-falconmesa-stratix-10.html

It seems like in your last reply you mentioned that you are able to communicate through the FPGA2HPS without any issues.

Are there any other issues before we close this case?

Regards

Jingyang, Teh

Mikhail_a

Occasional Contributor

2 years ago

Unfortunately as you can see there is an AXI4 spec violation as ARLEN is not zero and the number of returned data beats corresponds to ARLEN == 0

So I cant say the bridge works correctly

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RVALID is high after reset on Agilex 7 M-series F2H bridge

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