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Mikhail_a's avatar
Mikhail_a
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

RVALID is high after reset on Agilex 7 M-series F2H bridge

Hello I work with Agilex 7 M-series device and I see a strange behavior of F2H bridge. I see that after deasserting f2h rst_n RVALID and BVALID signal go high, also I see some data coming from RDATA...
Configuration
Artavazd's avatar
Artavazd
Icon for New Contributor rankNew Contributor
2 years ago

Hi

This piece of log

FPGA not ready. Bridge reset aborted!
...........FPGA reconfiguration OK!

goes from U-Boot as it tries to disable bridges before programming FPGA, after that it enables them and as enabling bridges was successful there are no more messages about it.

As I see bridges are configured alright, at least I'm able to use HPS to FPGA bridge with no issues.

To be honest I see no connection between HBM and FPGA2HPS bridge, they are completely separated IP and I don't think HBM can somehow help me here.

I haven't seen any AXI settings for FPGA2HPS bridge such as burst length, I thought it is just supposed to support lengths more than one.