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Mikhail_a's avatar
Mikhail_a
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

RVALID is high after reset on Agilex 7 M-series F2H bridge

Hello I work with Agilex 7 M-series device and I see a strange behavior of F2H bridge. I see that after deasserting f2h rst_n RVALID and BVALID signal go high, also I see some data coming from RDATA...
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Mikhail_a's avatar
Mikhail_a
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Some update

I've upgraded Quartus to 24.1, upgraded u-boot fsbl to 2023.10

and now I see that RVALID signal is low after reset, but It looks like ARLEN signal is not connected to where it should be. So on any read request the bridge returns only one transfer of data with RLAST high irrespective to any ARLEN I send. It looks like ARLEN is always zero right now.

EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,

I see in the old boot logs, the FPGA bridges are not setup yet:

How's the latest boot log using the latest Quartus and U-boot? Is the bridge configured properly now?

In the new U-boot, the bridge enable is added as per line 15 & 54:
u-boot-socfpga/drivers/fpga/altera.c at socfpga_v2023.10 · altera-opensource/u-boot-socfpga · GitHub

Okay, for these signal is more related to the HBM2 IP and how the AXI interface is defined(HBM2 IP UG):

https://www.intel.com/content/www/us/en/docs/programmable/683189/23-4-19-6-1/axi-user-interface-signals.html

As I couldn't find these signals in the HPS TRM for Agilex 7, for the ARLEN it is the burst length transaction (you may find it in the above link, "axi_0_0_arlen"). How is the HBM2 IP's setting on the burst length value?

Anyway, I am a bit caught up on my side and the HBM2 IP is new to me too, so I may provide my responses late.

Thanks for your patience.