Forum Discussion

Mikhail_a's avatar
Mikhail_a
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

RVALID is high after reset on Agilex 7 M-series F2H bridge

Hello I work with Agilex 7 M-series device and I see a strange behavior of F2H bridge. I see that after deasserting f2h rst_n RVALID and BVALID signal go high, also I see some data coming from RDATA...
Configuration
EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,

Are you using this board?:

https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/agm039.html

May I know how you boot up the board, using SD card etc?

Can you explain briefly how you perform the reset, is it thourgh the signal tap?

Also, if you do a power cycle of the board does the signal also behave the same?

If you are using the above aforementioned board, we have the GSRD for it:

https://www.rocketboards.org/foswiki/Documentation/AgilexSoCGSRDDEVAGM039F

Mikhail_a's avatar
Mikhail_a
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi!

You are right I use the exact same board.

I used this GSRD from the rocketboards as a reference. But as I found out its u-boot doesn't enable FPGA-HPS bridges, so I have to build u-boot as described here https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderAgilex7 while using the same kernel and fsbl binary as in mentioned GSRD.

I have a custom module that holds asserted reset for couple of minutes so I have time to enable signaltap and observe its deasserting. But even without this module I see that after ninit_done is asserted i have RVALID high. I see this issue every time I boot the board.