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Altera_Forum
Honored Contributor
Honored ContributorRTL of design is different from expected
I would like to implement a freq divider by using clock enable method(clock enable signal connect to every enable pin of register in design). however, when i write the verilog code e.g "...
Altera_ForumHonored Contributor
Honored ContributorTry this
(* keep = 1 *) wire my_clk_en = clk_ena && function_ena; always @ (posedge clk) begin if(my_clk_en) begin ... end end This way you'll be able to find the my_clk_en in TQ with get_keepers.
