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Altera_Forum's avatar
Altera_Forum
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15 years ago

RTL of design is different from expected

I would like to implement a freq divider by using clock enable method(clock enable signal connect to every enable pin of register in design). however, when i write the verilog code e.g "...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

FvM, the problem i faced is the name of output of comb logic is the name synthesized by QII. I cant constraint multicycle path on the every module i have 1 one shot. Any idea on it? Or this is the disadvantage of using clock enable method?