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Altera_Forum's avatar
Altera_Forum
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15 years ago

RTL of design is different from expected

I would like to implement a freq divider by using clock enable method(clock enable signal connect to every enable pin of register in design). however, when i write the verilog code e.g "...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The clock enable function is usually implemented in the combinational logic. The reason for it is simple: None of the recent Altera FPGA families has a dedicated clock enable input at it's core registers, check the device manuals.