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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Routing USB through FPGA

Hi, I'm having some difficulties routing USB through my DE-1 FPGA board. The goal is to make the FPGA chip look like a bare wire to an USB throughput. The thought was to have it perform the han...
BDarji's avatar
BDarji
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Hello,

This may be a bit off track but this may be useful to someone in future.

Here are the reasons why we need an external PHY chip.

(1) USB requires both differential and single ended signalling. Certain bus states are indicated by single ended signals. For example, single ended zero (SE0) is used to perform USB reset operation. It is generated by holding both D+ and D- lines at low. During data transfer, it uses differential signaling. In order to get more idea, you are requested to refer section 7.1 Signalling from USB2.0 Specification.

It shows high-speed capable transceiver circuit.

(2) It also uses some pull-up or pull-down registers. Either some pull-up registers or termination registers need to be attached or detached during run-time.

For example, after speed negotiation, high speed device needs to enable high speed terminations on both D+/D- lines and needs to remove pull-up resistor from D+ lines.