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Altera_Forum
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12 years ago

RMII receive timing at 10Mbit

This isn't entirely an FPGA question, but I can't seem to find the answer anywhere else. I am working on a project that is going to use a pair of 10/100 Ethernet PHYs on each end, along with a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

The standard states that RX_CRS/DV shall be asserted while the receive medium is non-idle. So, it should remain asserted throughout the frame, and you just need to sample every 10 cycles. You can verify with Signaltap.

Figure 2 in the spec has some diagrams about the toggle at 25MHz on a nibble boundary.