Rise/Fall delay

Hi all,

I've got a design where I want the QA output of an 8bit counter to have a rise/fall time delay. Something similiar to putting a capacitor to ground on the output line. I'd rather not add the capacitor to the board at this time.

I was looking at the properties of the 8bit counter in the design file and I saw a "Parameters" section. Is there something I can put in here to add a delay to the rise/fall time? I couldn't find any examples online of a sample parameter modification for a counter though.

I did do a search in the forums and I saw TCL commands etc, but I'd rather keep this as simple as possible since I don't have any other scripts.

I'm using Quartus 9.0sp2 due to the ACE1K fpga I'm using. I am however constrained to this setup.

Thanks in advance!