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Altera_Forum's avatar
Altera_Forum
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13 years ago

RISC architecture

Hi all

I am working on a RISC architecture which consists processing unit, control unit and memory unit. My problem is when I am putting all the three modules under one top module the RISC system is not showing any output but it is getting compiled. I checked with each individual module separately and then with the combination of two, but I did not understand why my top module which consists all the three i.e. processing unit, control unit and memory unit is not working.

If required I will post my codes too.

Can anyone please tell me the problem.

Thank you in advance.

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    Can anyone please tell me the problem.

    --- Quote End ---

    Do you have a testbench for your CPU? Have you simulated it in Modelsim? If not, its time to learn those tools.

    There's not much point in going to synthesis until you know your logic works correctly in simulation.

    If you've never used Modelsim before, there's a basic example in this thread

    http://www.alteraforum.com/forum/showthread.php?t=32386

    Try and create a testbench for your CPU, have it execute code, and see if you can track down your problem. If you cannot, then post your code, your testbench, and an explanation of the design. Members of this forum will provide advice.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thank you Dave for replying.

    I have a testbench and I simulated it in altera-modlesim but it is not showing me any output results. Do I need to use modelsim as a standalone simulator or altera-modelsim would allow me to do the job.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    How about posting some code? Questions like yours "Theres no output, my design isnt working" is not a very good question when we have no idea how the design or testbench work.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    Thank you Dave for replying.

    I have a testbench and I simulated it in altera-modlesim but it is not showing me any output results. Do I need to use modelsim as a standalone simulator or altera-modelsim would allow me to do the job.

    --- Quote End ---

    Modelsim-ASE is more than sufficient for your needs.

    As Tricky pointed out, post code so we can provide useful feedback.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Did you not notice there is a "Manage Attachments" button? Use that to add a zip file.

    Please delete the coding postings in the message boxes above, they clutter the thread (and have lost indentation/formatting). Your zip file should contain the source code and a script to run the simulation.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Thank you all for responding and giving valuable suggestions to my code.

    I sorted out the problem in seeing some outputs in modelsim.

    But the main problem I observed with my code is, it is not synthesizing. I am not able to view the design in the Technology map viewer except two pins (clk, rst) in the QUARTUS II 11.0, but I can see the complete design in the RTL viewer in the QUARTUS II 11.0.

    After compiling the code I observed the message in the info that

    "Info: 102 registers lost all their fanouts during netlist optimizations".

    Can anyone please tell me how to solve this problem and keep all my sub-modules without optimizing.