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Altera_Forum
Honored Contributor
Honored ContributorRISC architecture
Hi all I am working on a RISC architecture which consists processing unit, control unit and memory unit. My problem is when I am putting all the three modules under one top module the RISC syst...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Can anyone please tell me the problem. --- Quote End --- Do you have a testbench for your CPU? Have you simulated it in Modelsim? If not, its time to learn those tools. There's not much point in going to synthesis until you know your logic works correctly in simulation. If you've never used Modelsim before, there's a basic example in this thread http://www.alteraforum.com/forum/showthread.php?t=32386 Try and create a testbench for your CPU, have it execute code, and see if you can track down your problem. If you cannot, then post your code, your testbench, and an explanation of the design. Members of this forum will provide advice. Cheers, Dave
