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Altera_Forum
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13 years ago

RISC architecture

Hi all I am working on a RISC architecture which consists processing unit, control unit and memory unit. My problem is when I am putting all the three modules under one top module the RISC syst...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Thank you all for responding and giving valuable suggestions to my code.

I sorted out the problem in seeing some outputs in modelsim.

But the main problem I observed with my code is, it is not synthesizing. I am not able to view the design in the Technology map viewer except two pins (clk, rst) in the QUARTUS II 11.0, but I can see the complete design in the RTL viewer in the QUARTUS II 11.0.

After compiling the code I observed the message in the info that

"Info: 102 registers lost all their fanouts during netlist optimizations".

Can anyone please tell me how to solve this problem and keep all my sub-modules without optimizing.