RF filter with FPGA / CPLD

Some FPGAs have an ADC built in but it probably isn't going to provide the dynamic range and SNR that you want for a receiver application; read the specs carefully. While you probably want a higher end ADC for your front end, an internal ADC might get you started to prove your concept at low cost.

Watch out for aliasing. You will need an analog AAF on the front end before your ADC. A while back I worked on a design where we used the FPGA as the IF mixer and could select channels digitally. It was a fun project.