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Altera_Forum
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11 years ago

RF filter with FPGA / CPLD

Hello to all. first of all I hope not wrong section of this forum. I studied electronics, I know very well for C ++ and assembly MCU. in recent times I have found out what are the FPGA and CPL...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

You will need to see if the board has an ADC with a speed suitable to RF sampling requirement(sampling rule or undersampling). Then you will need to estimate your dsp requirements. I understand cyclone has 150 multipliers or so. You need to see how many taps you want and if you can go above signal speed to share resource.