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Altera_Forum
Honored Contributor
Honored ContributorRF filter with FPGA / CPLD
Hello to all. first of all I hope not wrong section of this forum. I studied electronics, I know very well for C ++ and assembly MCU. in recent times I have found out what are the FPGA and CPL...
Altera_ForumHonored Contributor
Honored ContributorYou need adc at a sampling speed compatible with RF signal.
You need fpga rather than cpld as you will require high speed and plenty of dsp resource depending on filter taps. crystal speed can be low as there are PLLs inside fpgas to generate high frequencies.
