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Rleduc's avatar
Rleduc
Icon for New Contributor rankNew Contributor
2 years ago

Retrieve clock signal in transceiver RX (High Speed Differential I/O) for Arria 10

Hello team,

I am currently using the Terasic HAN Pilot Plateform which uses Arria 10 FPGA-SoC. The board provides SFP+ connector, whose serial data TX/RX are assigned to High Speed Differential I/O (HSSIO) pins of the Arria 10's XCVR bank.

I am using the SFP to send (TX) a clock signal of 125MHz by overampling it at 1Gbps and 8 bit data "11110000". This work well since according to the a10 device handbook, the transceivers are allowed to be oversampled down to 125 MHz.

However, I don't really know how to retrieve this signal when I receive it with RX transceiver. I deserialize it and get a 8 bit parallel data reg. How do I create a clock signal from this ? Using an LVDS serializer ? This seems a pretty heavy solution to implement only to get my clock signal. Is there any other way to do this, probably a well known solution for this case that I'm not aware of ?

Thanks

4 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    2 years ago
    If you are sending source synchronous data between FPGA over gigabit link, you'll usually recover the clock on the RX site in the receiver IP and won't send a dedicated clock. What's exactly the purpose of the received clock?
  • Rleduc's avatar
    Rleduc
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hi,

    Yes, this is not the actual scenario here. Commonly we would provide an external 125 Mhz clock source, whose purpose is to drive synchronously an ADC board at this sampling rate and the FPGA board. The clock source is on the ADC board, so I need to send it through SFP to the FPGA for it to be synchronous, I cannot generate it locally. We don't have yet the SFP interface for the ADC board, so prior to get it I wanted to validate this point by generating the clock with SFP TX and looping it back on RX. Indeed this is pointless here since I generate the clock directly on FPGA, but this is only for debug purpose. In the future the FPGA needs to be synchronous to this external clock through SFP, or at least we want to aim that - provided this is technically doable !

    Regards

  • Kshitij_Intel's avatar
    Kshitij_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,


    Can you please share the following details.


    1. Which Operating system you are using?
    2. Which Quartus Software version you are using?
    3. Which device(OPN) you are targeting?


    Thank you

    Kshitij Goel



  • Kshitij_Intel's avatar
    Kshitij_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi,


    As we do not receive any response from you on the previous question that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    Thank you

    Kshitij Goel