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New Contributor

2 years ago

Retrieve clock signal in transceiver RX (High Speed Differential I/O) for Arria 10

Hello team, I am currently using the Terasic HAN Pilot Plateform which uses Arria 10 FPGA-SoC. The board provides SFP+ connector, whose serial data TX/RX are assigned to High Speed Differential I/O ...

FvM

Super Contributor

2 years ago

If you are sending source synchronous data between FPGA over gigabit link, you'll usually recover the clock on the RX site in the receiver IP and won't send a dedicated clock. What's exactly the purpose of the received clock?

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Retrieve clock signal in transceiver RX (High Speed Differential I/O) for Arria 10

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