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My guess is that the resistors are there to "idiot proof" the design.
If a switch is connected to 3.3V, and a user configures the FPGA with a design that accidentally drives a logic low on an FPGA pin configured to the switch, i.e., on a pin that should be configured as an input, then the series resistor will limit the current and save damaging the pin.
Older versions of Quartus would unfortunately set unused pins to ground, so this problem was easy to create.
Both versions of the DE2 board should have had these resistors on all pins that could be defined as I/O (the resistors would not be required on FPGA input-only pins).
Cheers,
Dave
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I didn't realized that SW0 to SW12 in DE2 board are connected to "dedicated clock input pins" from Cyclone II. Furthermore, with your explanation now I understand the design.
Thank you!
Honored Contributor
