Reset Vector - NIOS

Hi MK,

Any updates from your side?

Regards,

Kelly

Hello sstrell, Kelly,

Further questions from my side.

"1) You're getting the programming bitstream and processor code mixed up. You must have a .pof or something in some non-volatile memory to program the device itself and then you need the Nios processor code stored somewhere else, pointed to by the reset vector, to start running that code when the processing starts (or is reset)."

Q1) so let's say I have a .pof in some non-volatile memory, and the Nios CPU system design have chosen the reset vector memory as flash, then it's expected that the Nios processor code should be stored in the flash memory pointed by the reset vector offset address. Is my statement here, correct?

"2) You're forgetting the CE signal. And the 0x10000000 is the base address in the system design, not a physical address on the flash. That goes back to the offset value to access the physical location on the flash."

Q2) The base address in the qsys does not relate to the physical address on the flash, but the offset value relates to the actual physical address of the flash. Is this correct?. so, in my case, the expectation is there should be Nios processor code starting at 0x08b00000. Is this statement correct?

"Your code is running directly from Eclipse (debug mode) over the JTAG connection. Eventually, you have to put the code in flash (or wherever specified by the reset vector)."

Q3) In this scenario I had actually mentioned the reset vector memory as flash. So, in the debug mode over JTAG, where was my Nios code stored?

Q4) In the same scenario as Q3, once I change the offset address in the qsys for reset vector ( still retained the reset vector memory as flash), and then run from eclipse in debug mode, I saw that the system was running fine and I was able to ping successfully whenever I set the reset vector address in specific range, whereas in certain other reset vector address range, the eclipse debug mode could run only until auto negotiation, and ping could not proceed. So, it kind of got stuck. I could not understand this discrepancy and behavior. Any thoughts on this?

Thank you for clearing my doubts. The overall experiments I did have now boiled down to one final question from my side.

I have a qsys project with NIOS, TSE IP, MSGDMA and other components in the system. The objective of the project is to bring up the TCP/IP stack and perform a ping from host pc to NIOS. Few pointers about the experiment.

1) The reset vector offset was pointed to external flash memory.

2) The FPGA was configured with .sof file. The flash was not programmed with anything from our side. But the NIOS reset vector memory was chosen as flash and reset vector offset was pointed to a location in flash.

3) The NIOS was booted in debug mode from eclipse over JTAG.

4) The Eclipse project is a simple socket server template project from Intel.

The experiment turned out to be successful, but, with the following question that I still could not find a reasonable answer.

Q1) If the reset vector offset is set to be: 0x0000b020 in qsys, we can observe from Eclipse NIOS II console that auto negotiation is established, and ping is happening successfully. But if I just change one single parameter in my entire project, which is the reset vector offset to be let's say: 0x08b00000 , then we can see only that auto negotiation is passed, but ping is not happening. So, what direction would you think next? I understand it's difficult to give an answer without knowing what the code is doing. But I am just looking for a hypothesis, or possible scenarios on what could have caused this. Any inputs are welcome and would give me a new direction :).

Thank you

Hi MK,

By changing the reset vector offset changes the location of the reset vector relative to the memory module’s base address and might affect your designed system.

Here is a link for your reference: https://www.intel.com/content/www/us/en/docs/programmable/683836/current/reset-vector.html

I am glad your project is compiled and pinged successfully with the correct base address.

Hope this clarifies your doubts.

Thank you.

Regards,

Kelly

Hi Kelly,

In my scenario, I am using debugger option through JTAG to run NIOS. So as per the discussion so far and understanding, the NIOS code is stored nowhere and hence the reset vector offset should not disrupt or affect the designed system in anyway. So I am not quite convinced with your statement. Am I missing something?

Hi,

Sorry for misunderstanding. Yes, the NIOS code is stored nowhere and sent over JTAG via debugger.

Hope this clarifies your doubts. I will be setting this case to close pending in the next few days.

Thank you.

Regards,

Kelly

Hi Kelly,

Thanks for your clarification. May I know what is the meaning of "setting this case to close pending"?. Does it mean I will have to wait for someone to address or give additional comments?

Hi MK,

May I know what are the additional comments or clarification needed? Without looking at your code, I am not able to further give comments or support.

Close pending means I will not be able to support your queries after and the community will be there to help you with your further queries.

Thank you.

Regards,

Kelly

Hi Kelly,

I understand. You may close this ticket for now. I will reopen one if needed in future. Thanks for your support.

Hi,

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

Thank you.

Regards,

Kelly Jialin, GOH