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Hello Kaz,
Thank you for very good explanation. Could you help me to understand following sentence more clearly?
Could you elaborate this? Do you mean reset is released during 'setup' or 'hold' period of register 1 and hence it would take time much than Tco ( Tco - clock to output delay ) for register1 to provide stable output?
Regards,
Bhaumik
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not type2 but
Yes, type1 sync design violation is that of tSU/tH of reg1 (and yes tCO will be unpredictable)
My thoughts on “micro-details” of events inside a clocked flip is that there are two issues:
1) Any D input has to be sampled at clock edge.
Hence the input D should not be in transition near clock edge or else sampling will not “see” if input is high or low as it could be in gray area of signal level.
If input D is not changing then above does not apply obviously
2) The flip has to change Q output state. If above violation in 1 occurs then output may go wrong for sometime
That is 1+2 implies tSU/tH case
In case of type2 snc design (async reset), only issue 2 above applies as input D is not sampled until reset release. So if Q output state has to change during reset deassertion we could get the flip in same problem. If Q output state does not change then this violation is irrelevant.
This is recovery/removal case
However, I am not sure why both registers are reset as I think first register can be reset only and then the type2 reset synchroniser becomes very close to type1
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