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Altera_Forum's avatar
Altera_Forum
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18 years ago

Reset process on a XIO1100 PHY

Hi all, With the XIO1100 documentation, I tried to initialize it with a dev card based on Cyclone II. Unfortunately, I see with my logic analyzer that the signal PHY_STATUS is never de-asserted...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Please be aware that all the problems I had with the XIO 1100 are now resolved and if someone's got a question, I'll answer with pleasure. ;)

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I had a problem with XIO1100. Traininjg Sequence is not getticompleted.

My device is sending TS1 frames, but they are not received correctly by host. TI PHY is sending only 2 byte ( BC-F7 ) twice and then one full TS1

but with 3rd,4th byte and last 2 bytes corrupted instead of 3 TS1 correct

frames. This is repeated every 3 TS1 frames.

Did you face this/similar problem ?

Thanks,

Vinayak.