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Altera_Forum
Honored Contributor
Honored Contributorreset MAX II
hi, i would like to know if i can rely on the power-on-reset of MAX II to know the initial values of the outputs? or should i use external reset? thanks sharen
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- This issue was discussed in heated recent threads. In short, no it is unreliable but yes it is, provided you exercise some care. The power-up values themselves are reliable(provided you set its Don't care off) since async reset is applied soon after configuration phase. The problem is that it is released non-synchronised to clk(or clks) and hence may upset your design at startup. To overcome that generate your own internal reset(depending on powerup values being 0 e.g. a counter), then apply it as usual to async ports (after being synchronised to its clk) --- Quote End --- So, if I understood you right, it sounds like it would be quite simple to use a two-flop reset synchronizer for this. I can have two flops with a initial state 0 and no reset pin. They should come up as zero. Then the fitst flop goes to the second one and the second one goes to the resets of all other flops. Then it resets asynchronously because of the CPLD`s internal mechansim and then come out synchronously with two clocks. -G
