I am working on a project involving Arria V FPGA. I need to have a PLL for generating clocks for my internal FPGA logic. I am confused about the reset signal of PLL. I have no external H/W reset pin. To which pin must I connect this reset signal. I am deriving the reset signal for logics from PLL locked signal. I am thinking of connecting this pin to POR signal. How to access the power on reset pin? Are there any other suggestions for connecting PLL reset pin? Thanks

I don't know Arria V, but with other Altera FPGA devices the PLL reset signal is optional. You expose and connect it only in special situation, i.e. when you need to reconfigurate the PLL or when you switch off a clock and have to resynchronize.

Thank you Cris. I am using Quartus 12.0 ver and here I have no option of disabling the reset pin. Is it suggested that I always connect this pin to logic low?

Having just checked (I assumed the same as Cris) it seems the reset input port is 'required' for the Altera PLL suitable for Arria V - see the user guide (https://www.altera.com/en_us/pdfs/literature/ug/altera_pll.pdf). A quick play with Quartus confirms this. POR pin? There isn't one - only an internal POR circuit for the device. I don't think there's any access to it. So, if tying reset to '0' isn't sufficient and you must generate a reset, I suggest you consider a counter that generates a reset at power up. And, if the PLL ever looses lock you can consider resetting the counter to regenerate the reset. Cheers, Alex

Hi Nagakiran, The reset to PLL is important especially after the PLL lose lock, or there is any change to the refclk, or dynamic reconfiguration performed. You can create some user logic to control the reset when these three events occur.

In a similar situation, I have no HW reset pin so I was planning to use loss of lock to drive a reset to the PLL, and also reset the all the registers in my design to a known state. Does it make sense to do that? I'm wondering if it's even necessary to do this, but I've never coded an FPGA without a reset.

Reset for PLL | Altera Community

12 Replies

Altera_Forum
Honored Contributor
8 years ago
There must be some official response from Intel about this somewhere. I can only imagine it's a very common question. Here are two solutions I have been using and found to work:

- Connecting the reset port to an external pin tied to ground on the PCB
- Using the PLL reference clock to generate a registered reset signal (e.g., using a counter or shift register)

The second solution could be expanded to reassert reset when lock is lost, however I thought this was precisely what the auto-reset setting was for, and hence I see no reason why Quartus does not allow you to tie reset to zero internally as in older families.
PNaja
New Contributor
7 years ago
I also have the same issue when I upgraded from Quartus 17.1 to 18.01 and later on to 18.1.
The initial converted Arria 10 load compiled successfully
Then I changed NIOS clock from my device_clk (connected to external pin) to a clock bridge connected to 100 MHZ external clock trying to reduce the clock to the NIOS max clock rate of 50 Mhz. This change was done in the platform designer.
The RST_N error message is pointing to the two PLL's that were instantiated in the top level design and is not showing up in the platform designer.
The change had nothing to do with the PLL, Why are we getting compile error on the part of the design that was not changed.

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Reset for PLL

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