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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Reset for PLL

I am working on a project involving Arria V FPGA. I need to have a PLL for generating clocks for my internal FPGA logic. I am confused about the reset signal of PLL. I have no external H/W reset...
PNaja's avatar
PNaja
Icon for New Contributor rankNew Contributor
7 years ago

I also have the same issue when I upgraded from Quartus 17.1 to 18.01 and later on to 18.1.

  • The initial converted Arria 10 load compiled successfully
  • Then I changed NIOS clock from my device_clk (connected to external pin) to a clock bridge connected to 100 MHZ external clock trying to reduce the clock to the NIOS max clock rate of 50 Mhz. This change was done in the platform designer.
  • The RST_N error message is pointing to the two PLL's that were instantiated in the top level design and is not showing up in the platform designer.
  • The change had nothing to do with the PLL, Why are we getting compile error on the part of the design that was not changed.