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tedh4ddv's avatar
tedh4ddv
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Remote Update for Cyclone 10 LP - CSR

Using Platform Designer, we've combined three IP Cores in a Cyclone 10 LP project to accomplish three functions: 1) allow an external processor access to the FPGA via a SPI bus 2) write a .jic file...
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mabdrahi's avatar
mabdrahi
Icon for Contributor rankContributor
2 years ago

Hi,


Remote Update FPGA IP core input clock (fMAX) values should 10 MHz—for Arria II and Stratix IV devices

20 MHz—for other supported devices


You can check the clock is it in this range?