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tedh4ddv's avatar
tedh4ddv
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Remote Update for Cyclone 10 LP - CSR

Using Platform Designer, we've combined three IP Cores in a Cyclone 10 LP project to accomplish three functions:
1) allow an external processor access to the FPGA via a SPI bus
2) write a .jic file to the serial flash configuration device (file is comprised of 2 .sof images)
3) initiate a reconfiguration of the FPGA to the alternate .sof image stored in the flash device.

The three IP Cores are:
1) Generic Serial Flash Interface
2) Remote Update
3) SPI Slave to Avalon Master Bridge

The project compiles successfully, and the FPGA boots to the .sof image located at flash address 0x0.

For test purposes, the platform also contains a scratch register implemented with the PIO (Parallel I/O) IP Core.

The scratch registers are read/write accessible which indicates that the SPI Slave to Avalon Master Bridge is operational.

We are having an issue with the Remote Update function. It appears we can write to the RU_BOOT_ADDRESS (offset 0x10) in the CSR space, but a read of this address consistently returns 0x0000_0000.

Additionally, when we attempt to initiate a reconfiguration, it does not occur. The procedure we are using is:
1) Write the value (0x0040_0000, in this case) to the RU_BOOT_ADDRESS register (offset 0x10).
2) Write the value 0x1 to the RU_RECONFIG register (offset 0x1D).

Is this the correct procedure to initiate a reconfiguration or are there additional steps we've overlooked?

Configuration

5 Replies

  • mabdrahi's avatar
    mabdrahi
    Icon for Contributor rankContributor
    2 years ago

    Hi,


    Thanks for the detail, while im try to read and understand your request, May i know where do you get the GHRD and for this project? (example rocketboard)


  • mabdrahi's avatar
    mabdrahi
    Icon for Contributor rankContributor
    2 years ago

    Hi,


    Remote Update FPGA IP core input clock (fMAX) values should 10 MHz—for Arria II and Stratix IV devices

    20 MHz—for other supported devices


    You can check the clock is it in this range?





  • tedh4ddv's avatar
    tedh4ddv
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    I am using a 20MHz clock. Generated from a PLL within the FPGA.

  • tedh4ddv's avatar
    tedh4ddv
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    This design is not based on any GHRD. It is a custom platform built using Quartus Prime Standard version 20.1. With help from an FAE at Arrow Electronics, we've got the CSR addressing straightened out. I can now read back what is written to the base address register... mostly. I do lose the bottom two bits of the data. Now, when I set the RU_RECONFIG bit, the FPGA seems to attempt a reconfiguration, but it fails to complete. There is a Watchdog Timeout indication in the status register.