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tedh4ddv's avatar
tedh4ddv
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2 years ago

Remote Update for Cyclone 10 LP - CSR

Using Platform Designer, we've combined three IP Cores in a Cyclone 10 LP project to accomplish three functions: 1) allow an external processor access to the FPGA via a SPI bus 2) write a .jic file...
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tedh4ddv's avatar
tedh4ddv
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

This design is not based on any GHRD. It is a custom platform built using Quartus Prime Standard version 20.1. With help from an FAE at Arrow Electronics, we've got the CSR addressing straightened out. I can now read back what is written to the base address register... mostly. I do lose the bottom two bits of the data. Now, when I set the RU_RECONFIG bit, the FPGA seems to attempt a reconfiguration, but it fails to complete. There is a Watchdog Timeout indication in the status register.