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YSuzu21
New Contributor
New ContributorRemote System Upgrade for MAX 10 FPGA
「AN 741: Remote System Upgrade for MAX 10 FPGA Devices over UART with the Nios II Processor」の「Figure 1. Reference Design Block Diagram」では、NiosⅡを使用してDual Configuration IP Core を制御しておりますが、、NiosⅡとDual ...
Thank you for your reply.
ShafiqY_Intel
Frequent Contributor
Frequent ContributorHi YSuzu21,
We use the same clock for NIOS II and Dual Configuration IP.
we use similar PLL output to these NIOS II IP and Dual Configuration IP:
Cheers
YSuzu21New Contributor
New ContributorThank you for your reply.
