Honored ContributorWe are trying to divide the complete data available, in row buffers of different size, and try implementing parallel processing, by calling the row buffers as individual separate entities. But, implementing the same is creating issue, and the data is not getting read in different row buffers. Can somebody suggest with some solution or white paper which has discussed this?
Honored ContributorIts not clear really what you want? are you doing a software or firmware solution? what code are you using? what is the problem? how have you tested the algorithm?
Honored ContributorIts still not clear what you're doing. Is it a software solution or firmware on an FPGA?
Honored ContributorHonored ContributorFor a start, this is an altera forum, for xilinx specific problems you're best going to the xilinx website.
But as a more general response - is your image a single image or video? how is it read? 256x256 is quite small and should easily be processeable in a single chunk.Honored ContributorIf its a Xilinx chip, you cannot use altera quartus (Quartus only compiles for Altera devices, Xilinx is a competing company).
What you need is some mechanism to read the data out of a memory - all you need is a single stream of data. For a 3x3 convolution you will need 2 line buffers. Given you say you have to move from one frame to the next, I assume you're working on video? why do you even need to store the image, you can just process it as it passes through the FPGA. Again, just 2 line buffers required, but you dont need a frame buffer. There is no need to break the image down into any chunks, with or without a frame buffer. You just stream it out pixel by pixel and processes it as you read it.
