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New ContributorRegarding Cyclone 10 LP AS Configuration Timing Parameters
We are currently planning to verify the configuration between Cyclone 10 LP and an external Flash ROM.
In order to confirm whether the Flash side specifications (setup / hold, tSLCH, etc.) are satisfied, we need to check the following timing parameters. However, these values are not described in the Cyclone 10 LP Datasheet.
Could you please share any available information on the following?
- Minimum values (ns) of DCLK High time and DCLK Low time
- Minimum and maximum delay time (ns) from the DCLK edge to when the data output (e.g., ASDO) changes
- Time (ns) from nCSO going Low to the first DCLK edge
- Time (ns) from the last DCLK edge to nCSO going High
Any information or reference document you can provide would be greatly appreciated.
Best regards,
1 Reply
FakhrulA_alteraRegular Contributor
Hi mario,
Thank you for your question.
For Cyclone 10 LP AS configuration mode, the public datasheet only specifies the AS DCLK frequency range. The documented DCLK range is 20 MHz to 40 MHz, with 33 MHz typical. Cyclone® 10 LP Device Datasheet
The specific timing items below are not separately specified in the Cyclone 10 LP datasheet:
- DCLK high time and low time minimum values
- Delay from DCLK edge to ASDO data change
- Time from nCSO Low to the first DCLK edge
- Time from the last DCLK edge to nCSO High
Because these values are not published, we cannot provide guaranteed min/max timing numbers for them.
For Flash ROM selection, please make sure the Flash device can support the Cyclone 10 LP AS DCLK frequency range, especially the maximum 40 MHz operating point. If your design requires guaranteed detailed pin timing, we recommend verifying this on the actual board or raising a formal support request for further review.
Best regards,
Fakhrul
