Regarding Cyclone 10 LP AS Configuration Timing Parameters

We are currently planning to verify the configuration between Cyclone 10 LP and an external Flash ROM.
In order to confirm whether the Flash side specifications (setup / hold, tSLCH, etc.) are satisfied, we need to check the following timing parameters. However, these values are not described in the Cyclone 10 LP Datasheet.

Could you please share any available information on the following?

1. Minimum values (ns) of DCLK High time and DCLK Low time
2. Minimum and maximum delay time (ns) from the DCLK edge to when the data output (e.g., ASDO) changes
3. Time (ns) from nCSO going Low to the first DCLK edge
4. Time (ns) from the last DCLK edge to nCSO going High

Any information or reference document you can provide would be greatly appreciated.

Best regards,