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5 Replies
- Altera_Forum
Honored Contributor
--- Quote Start --- hi The circuit is attached. how can I solve this error? Thanks --- Quote End --- The output of the register is not used. So it is removed by the synthesis tool. kind regards GPK - Altera_Forum
Honored Contributor
Hi pletz
even the output of register is connected, it is giving the same error kind regards - Altera_Forum
Honored Contributor
the JKFF inst 4 with J and K at VCC will toggle Q each positive clock edge.
so the output of inst4 is half the clock rate inst 3 has K at GND and J connected to Q of the toggling inst 4 JKFF the output Q should take over the input information with every positive clock edge so if your output is connected the circuit should work as you said, "inst3 ist reduced with stuck..." could you please add the complete message ? - Altera_Forum
Honored Contributor
Hi
Warning (14130): Reduced register "inst3" with stuck data_in port to stuck value VCC kind regards - Altera_Forum
Honored Contributor
--- Quote Start --- Hi Warning (14130): Reduced register "inst3" with stuck data_in port to stuck value VCC kind regards --- Quote End --- J K Q L L Qo Qo = level of Q before clock pulse H L H L H L H H Toggle Have look to the part of the trues table. You connect the K input to "L". Q can only stay on the old level or in case of J = "H" can go to "H". After going to high it will never change. Kind regards GPK