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Altera_Forum
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8 years ago

Reduce clock frequency when system clock is dynamic

Hi, I would like to know a method to divide the clock to a certain frequency. I am aware of different methods of clock divider but the thing here is that the on-board system clock is dynamic (not fix...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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The internal UFM oscillator block is NOT programmable in frequency. The spec is that it may be anywhere between 3.9 and 5.3 MHz on a device, so you get what you get, and have to accept that variability. The Altera/Intel MaxV device datasheet has all the details about the internal oscillator specs and usage.

So, if I understand it correctly I can not guess/calculate the accurate frequency of the internal clock? I have read that I can calculate the relative frequency the CPLD will run on and take that as an accurate constant clock. Can that be true?