Reduce clock frequency when system clock is dynamic

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Thanks! Could you give a reference about frequency variation of the UFM oscillator, so I can read more about it? I found the details about 3.9-5.3 MHz, but not about not being programmable and the frequency variations. Also is the internal oscillator in the UFM block the only oscillator option for 5m160ze64 or does it consist of another on-board oscillator?

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The internal UFM oscillator block is NOT programmable in frequency. The spec is that it may be anywhere between 3.9 and 5.3 MHz on a device, so you get what you get, and have to accept that variability. The Altera/Intel MaxV device datasheet has all the details about the internal oscillator specs and usage.

The UFM oscillator is the ONLY internal oscillator for that device. Any other 'on board' oscillator would have to be provided/designed into the BOARD your CPLD device is located on. You don't say where you are using a standard development board, or if this is a custom board design done by you or someone else. So it is up to your board/system designer to provide any other clock reference into your part.