Receiver to FPGA

Serial data transmission depends on protocols. You have to select a suitable protocol than can be decoded at the FPGA side. Stratix III and IV FPGA offer a soft CDR feature with fast serial receiver channels that can be helpful to decode synchronous data streams. Using asynchronous (UART) protocols would be another option.

The output of the Linear demo circuit is apparently an amplified analog photo diode signal. It has to be converted to a digital data stream by a suitable circuit, e.g. a comparator. It might be possible to "abuse" a Stratix LVDS receiver as comparator, but the output voltage of the TIA must be limited to a safe FPGA input range before.