Receiver clock recovery

Hi all,

First any contribution from experienced engineers appreciated.

I am heading to design a receiver for qpsk/16qam of up to 280Msps.

The received signal will be upsampled by 2 to a staggering 560MHz for the receiver front end. I am supposed to design the clock recovery at this speed in an fpga !!

To begin with and to be realistic, I want to run the fpga at 280MHz only using parallel processing except may be at certain muxing points. I don't foresee I can run the fpga at 560MHz except for such tiny areas.

The most demanding task is the timing recovery which is to be in a fully digital way(fixed clock, no PLL)

Now my plan:

Matched filter => timing recovery => carrier recovery...

The timing recovery must therfore be tolerant to carrier residue.

I made a research and came to this timing recovery circuit:

signal after matched filter to be passed through "fractional delay filter", output of this goes into TED(timing error detector), this is fedback to control the fractional delay through a filter.

My research showed that people have used Gardner algorithm for TED.

The questions:

Does anybody have experience with Gardner algorithm, does it work for qpsk/16qam well and under what condtions(incidentally there is a simulink block for this algorithm and others).

My understanding of this algorithm is this:

It works on 2 samples per symbol and looks for symbol enegy gradient and checks against any shift from expected trajectory. It is implemented as:

error = (last symbol - current symbol) * midsample.

This error is then used to delay/advance the signal in an interpolator(that does delay only, no up/down sampling)

Does anybody have experience with fractional delay interpolator. I know Farrow filter is popular. Are there alternatives?

Any contributions welcomed.