Realization MFM de/en-Coder via MAXII

Hello @ All,

I'm new here and I hope that someone can help me concerning matter above.

Background: I work almost honorary in my spare time for the computer museum in Munich and my goal is to transfer vintage Computer/Storage to new technology like FPGA and ARM-7 MCU.

For more details, I want to refer to my homepage .

Right now, I have a big hurdle:confused:: Realizing mfm encoders and decodersin the FPGA/MAXII. I haven't found the right references until now. I am working here with a magnetic device with all the preemphasis stuff and phase shifting around and this is really a piece of complicated hardware ( for me ). To rebuild this piece of hardware in FPGA related to the RLV-12 engineering drawings, it is still not clear to me how to realize the 5nsec delay logic in the FPGA and furthermore I don't know the ROM code for the phase-moving logic to get it in the FPGA. It is also not clear yet whether I need this all.

My question:

1. Has someone references how to get implemented a MFM de/en-Coder logic in FPGA?

2. How can I realize a 9x 50nsec delay in FPGA?

3. How can I implement a ROM , 32x8bit in FPGA?

My environment:

Quartus II 9.1 Web Edition Software

MAXII-Micro-kit-Board

( more details on my homepage , chapter 1.4 )

Best regards from Germany/Munich and many thanks in advance,

Reinhard