Forum Discussion
Occasional ContributorReading HPS EMAC counters not reliable
UPDATE: Seems EMAC1 is looking OK. The problem, there, was understanding what's meant by "good" in some cases. But EMAC0 looks like it's almost not counting anything. It's quite sporadic when I see anything increment, and this is while sending thousands of packets in/out of it.
------------------- original message, below ---------------
I'm using both HPS EMACs on a design and want to use the counters in them for various purposes. For example, 0xff700180 and 0xff702180 should be frame counters for EMAC0 and EMAC1, respectively.
But when I send a packet to EMAC0, I don't see this counter increment. And when I send, say 10, packets to EMAC1, it counts 3. I know the packets are being sent as they arrive at the destinations just fine, but the EMAC is not counting.
The same for other counters. In the above example, they are UDP packets. But the IP4 and UDP counters are not incrementing by the right number, either.
I'm using DS-5 debugger to read these registers/memory, as well as saving them in variables in my program code and these agree with each other, but are clearly wrong.
Any ideas? Has anyone seen these counters work, properly?
(I am able to read/write status registers and such, just fine, but these counters seem broken.)
Final answer... Set the PR bit, not the RA bit. One does not need both, but the PR bit is the correct one if one wants counters to work. No documentation on this, sadly, but that's what we've deduced.
15 Replies
FawazJ_AlteraFrequent Contributor
Hello Dzar,
this is not the expected behavior. By default, the counter register should reflect the number of frames, whether good or bad.
Let me investigate about these counters. I will post my feedback once I find more information about it,
thanks
- Dzar
I guess I don't understand why that link is useful. First, it's for Stratix 10 devices, and I'm using Cyclone V. But assuming the EMAC designs are identical, that document is about how to integrate the PHY and configure the system.
My system "works." That is, I can send and receive millions of packets, at line rate (100 Mb/s in my case) with no issues. The only problem I seem to have is that when I read the counters in EMAC0, I see obviously wrong numbers. EMAC1 counters seem correct, however.
Is there a known issue with EMAC0 counters? What are some configuration issues with it that I may have overlooked repeated to the counters. The both seem to work very well in TX/RX, otherwise. I use the same configuration code for both devices. One works and the other doesn't.
Ahmed_H_Intel1Hi,
Can you please ensure your design includes the necessary Intel settings to configure the HPS EMAC outputs for the required delays? This might be the reason.
Here you can find very useful guidelines
- Dzar
These are Cyclone V SE parts: 5CSEBA2U23I7N for example. Dual ARM.
- FawazJ_Altera
Hello,
Which device is this?
Thanks
